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36-mbit (1m x 36/2m x 18/512k x 72) pipelined sync sram cy7c1440av33 cy7c1442av33 cy7c1446av33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05383 rev. *e revised june 23, 2006 features ? supports bus operation up to 250 mhz ? available speed grades are 250, 200 and 167 mhz ? registered inputs and outputs for pipelined operation ? 3.3v core power supply ? 2.5v/3.3v i/o power supply ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? provide high-performance 3-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? single cycle chip deselect ? cy7c1440av33, cy7c1442av33 available in lead-free 100-pin tqfp package, lead-free and non-lead-free 165-ball fbga package. cy7c1446av33 available in lead-free and non-lead-free 209-ball fbga package ? also available in lead-free packages ? ieee 1149.1 jtag-compatible boundary scan ? ?zz? sleep mode option functional description [1] the cy7c1440av33/cy7c1442a v33/cy7c1446av33 sram integrates 1m x 36/2m x 18 and 512k x 72 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1440av33/cy7c1442av33/cy7c1446av33 operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 250 mhz 200 mhz 167 mhz unit maximum access time 2.6 3.2 3.4 ns maximum operating current 475 425 375 ma maximum cmos standby current 120 120 120 ma note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 2 of 31 logic block diagram ? cy7c1440av33 (1m x 36) address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control logic block diagram ? cy7c1442av33 (2m x 18) [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 3 of 31 bw d bw c bw b bw a bwe gw ce1 ce2 ce3 oe enable register pipelined enable address register adv clk binary counter clr q1 q0 adsp adsc mode a 0, a1,a a[1:0] bw f bw e bw h bw g dqs dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h output registers memory array output buffers e dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver input registers byte ?a? write driver dq e , dqp e write driver dq f , dqp f write driver dq g , dqp g write driver dq h , dqp h write driver sense amps sleep control zz dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver dq e , dqp e write driver dq f , dqp f write driver dq f , dqp f write driver dq h , dqp h write driver logic block diagram ? cy7c1446av33 (512k x 72) [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 4 of 31 pin configurations dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1440av33 (1m x 36) nc a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1442av33 (2m x 18) nc 100-pin tqfp pinout a a a a a a 1 a 0 nc/72m a v ss v dd a a a a a a a a mode a [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 5 of 31 pin configurations (continued) 165-ball fbga (15 x 17 x 1.4 mm) pinout cy7c1440av33 (1m x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1442av33 (2m x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 6 of 31 209-ball fbga (14 x 22 x 1.76 mm) pinout cy7c1446av33 (512k 72) pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dq g dq g dq g dq g dq g dq g dq g dq g dq c dq c dq c dq c nc dqp g dq h dq h dq h dq h dq d dq d dq d dq d dqp d dqp c dq c dq c dq c dq c nc dq h dq h dq h dq h dqp h dq d dq d dq d dq d dq b dq b dq b dq b dq b dq b dq b dq b dq f dq f dq f dq f nc dqp f dq a dq a dq a dq a dq e dq e dq e dq e dqp a dqp b dq f dq f dq f dq f nc dq a dq a dq a dq a dqp e dq e dq e dq e dq e a adsp adv a nc nc nc/72m aa a a aa aa a a1 a0 a aa aa a nc/144m nc/288m nc/576m gw nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc v ss v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adsc bw v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a1: a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes ar e written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 7 of 31 ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not av ailable for aj package version. not connected for bga. where referenced, ce 3 is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high , i/o pins are tri-stated, and act as input data pins. oe is masked during the first cl ock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data int egrity preserved. for no rmal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the co re of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being utilize d, this pin should be disconnec ted. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to th e jtag circuitry . if the jtag featur e is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. nc/72m, nc/144m , nc/288m, nc/576m and nc/1g are address expansion pins ar e not internally connected to the die. pin definitions (continued) name i/o description [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 8 of 31 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.6ns (250-mhz device). the cy7c1440av33/cy7c1442av33/cy7c1446av33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processo rs that utilize a linear burst sequence. the burst order is user selectable, and is deter- mined by sampling the mode i nput. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate thro ugh the output register and onto the data bus within 2.6 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the firs t cycle of the access. after the first cycle of the access, the ou tputs are controlled by the oe signal. consecutive single r ead cycles are supported. once the sram is deselected at clo ck rise by the chip select and either adsp or adsc signals, its output will tri-state immedi- ately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses re quire two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs inpu ts is written into the corre- sponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1440av33/cy7c1442av33/cy7c1446av33 provides byte write capability that is described in the write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, will selectively write to only the des ired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1440av33/cy7c1442av33/cy7c1446av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatical ly tri-stated whenever a write cycle is detected, regardle ss of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1440av33/cy7c1442av33/cy7c1446av33 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are automatical ly tri-stated whenever a write cycle is detected, regardle ss of the state of oe . burst sequences the cy7c1440av33/cy7c1442av33/cy7c1446av33 provides a two-bit wraparound counter, fed by a1: a0, that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise will automati- cally increment the burst counter to the next address in the burst sequence. both read an d write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 9 of 31 interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 100 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [2, 3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tri-state deselect cycle, power down none l l x l l x x x x l-h tri-state deselect cycle, power down none l x h l l x x x x l-h tri-state deselect cycle, power down none l l x l h l x x x l-h tri-state deselect cycle, power down none l x h l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q notes: 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only 2 chip selects ce 1 and ce 2 . 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low). [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 10 of 31 read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d truth table (continued) [2, 3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq truth table for read/write [4,8,9] function (cy7c1440av33) gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? (dq a and dqp a ) hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c ) hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d ) hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx truth table for read/write [4, 8, 9] function (cy7c1442av33) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x notes: 8. bw x represents any byte write signal. to enable any byte write bw x , a logic low signal should be applied at clo ck rise.any number of bye writes can be enabled at the same time for any given write. 9. table only lists a partial listing of the by te write combinations. any combination of bw x is valid. appropriate write will be don e based on which byte write is active. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 11 of 31 ieee 1149.1 serial boundary scan (jtag) the cy7c1440av33/cy7c1442av33/cy7c1446av33 incor- porates a serial boundary scan test access port (tap). this part is fully compliant with ieee standard 1149.1. the tap operates using jedec-standard 3. 3v or 2.5v i/o logic levels. the cy7c1440av33/cy7c1442av33/cy7c1446av33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any regist er. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram truth table for read/write [4, 8, 9] function (cy7c1446av33) gw bwe bw x read hhx read h l all bw = h write byte x ? (dq x and dqp x )hll write all bytes h l all bw = l write all bytes l x x test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 12 of 31 performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this rese t does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr st ate. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap c ontroller is in the capture-dr state, a snapshot of data on th e inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap ma y then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 13 of 31 the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruct ion is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system output pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bu s into a tri-state mode. the boundary scan register has a special bit located at, bit #89 (for 165-fbga package) or bit #138 (for 209-fbga package). when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 14 of 31 3.3v tap ac test conditions input pulse levels ........... .................................... v ss to 3.3v input rise and fall times ........... ........... ..............................1ns input timing reference levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply voltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels................................................ .v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels...... ............. ......................1.25v output reference levels ............. ..... ..............................1.25v test load termination supply voltage .................... ........1.25v 2.5v tap ac output load equivalent notes: 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. tap ac switching characteristics over the operating range [10, 11] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 15 of 31 tap dc electrical characteristics and operating conditions (0c < ta < +70c; v dd = 3.135 to 3.6v unless otherwise noted) [12] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma, v ddq = 3.3v 2.4 v i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1440av33 (1m x 36) cy7c1442av33 (2m x 18) cy7c1446av33 (512k x 72) description revision number (31:29) 000 000 000 describes the version number. device depth (28:24) [13] 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 000000 000000 000000 defines memory type and architecture bus width/density(17:12) 100111 010111 110111 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 1 1 indicates the presence of an id register. scan register sizes register name bit size (x36) bit size (x18) bit size (x72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order (165-ball fbga package) 89 89 ? boundary scan order (209-ball fbga package) ? ? 138 identification codes instruction code description extest 000 captures the i/o ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. notes: 12. all voltages referenced to v ss (gnd). 13. bit #24 is ?1? in the id register definition s for both 2.5v and 3.3v ve rsions of this device. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 16 of 31 notes: 14. balls that are nc (no connect) are preset low. 15. bit# 89 is preset high. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. identification codes (continued) instruction code description 165-ball fbga boundary scan order [14,15] cy7c1440av33 (1m x 36), cy7c1442av33 (2m x 18) bit # ball id bit # ball id bit # ball id bit # ball id 1 n6 26 e11 51 a3 76 n1 2 n7 27 d11 52 a2 77 n2 3n10 28g10 53b2 78p1 4p11 29f10 54c2 79r1 5 p8 30 e10 55 b1 80 r2 6 r8 31 d10 56 a1 81 p3 7r9 32c11 57c1 82r3 8p9 33a11 58d1 83p2 9p10 34b11 59e1 84r4 10 r10 35 a10 60 f1 85 p4 11 r11 36 b10 61 g1 86 n5 12 h11 37 a9 62 d2 87 p6 13 n11 38 b9 63 e2 88 r6 14 m11 39 c10 64 f2 89 internal 15 l11 40 a8 65 g2 16 k11 41 b8 66 h1 17 j11 42 a7 67 h3 18 m10 43 b7 68 j1 19 l10 44 b6 69 k1 20 k10 45 a6 70 l1 21 j10 46 b5 71 m1 22 h9 47 a5 72 j2 23 h10 48 a4 73 k2 24 g11 49 b4 74 l2 25 f11 50 b3 75 m2 [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 17 of 31 note: 16. bit# 138 is preset high. 209-ball fbga boundary scan order [14, 16] cy7c1446av33 (512k x 72) bit # ball id bit # ball id bit # ball id bit # ball id 1 w6 36 f6 71 h6 106 k3 2 v6 37 k8 72 c6 107 k4 3 u6 38 k9 73 b6 108 k6 4 w7 39 k10 74 a6 109 k2 5v7 40j11 75a5 110l2 6 u7 41 j10 76 b5 111 l1 7t7 42h11 77c5 112m2 8 v8 43 h10 78 d5 113 m1 9 u8 44 g11 79 d4 114 n2 10 t8 45 g10 80 c4 115 n1 11 v9 46 f11 81 a4 116 p2 12 u9 47 f10 82 b4 117 p1 13 p6 48 e10 83 c3 118 r2 14 w11 49 e11 84 b3 119 r1 15 w10 50 d11 85 a3 120 t2 16 v11 51 d10 86 a2 121 t1 17 v10 52 c11 87 a1 122 u2 18 u11 53 c10 88 b2 123 u1 19 u10 54 b11 89 b1 124 v2 20 t11 55 b10 90 c2 125 v1 21 t10 56 a11 91 c1 126 w2 22 r11 57 a10 92 d2 127 w1 23 r10 58 c9 93 d1 128 t6 24 p11 59 b9 94 e1 129 u3 25 p10 60 a9 95 e2 130 v3 26 n11 61 d7 96 f2 131 t4 27 n10 62 c8 97 f1 132 t5 28 m11 63 b8 98 g1 133 u4 29 m10 64 a8 99 g2 134 v4 30 l11 65 d8 100 h2 135 5w 31 l10 66 c7 101 h1 136 5v 32 k11 67 b7 102 j2 137 5u 33 m6 68 a7 103 j1 138 internal 34 l6 69 d6 104 k1 35 j6 70 g6 105 n6 [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 18 of 31 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.3v to +4.6v supply voltage on v ddq relative to gnd ...... ?0.3v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ?5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [17, 18] dc electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3v i/o 3.135 v dd v for 2.5v i/o 2.375 2.625 v v oh output high voltage for 3.3v i/o, i oh = ? 4.0 ma 2.4 v for 2.5v i/o, i oh = ? 1.0 ma 2.0 v v ol output low voltage for 3.3v i/o, i ol = 8.0 ma 0.4 v for 2.5v i/o, i ol = 1.0 ma 0.4 v v ih input high voltage [17] for 3.3v i/o 2.0 v dd + 0.3v v for 2.5v i/o 1.7 v dd + 0.3v v v il input low voltage [17] for 3.3v i/o ?0.3 0.8 v for 2.5v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 475 ma 5-ns cycle, 200 mhz 425 ma 6-ns cycle, 167 mhz 375 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc all speeds 225 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 120 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc all speeds 200 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 135 ma notes: 17. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 18. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 19 of 31 capacitance [19] parameter description test conditions 100 tqfp max. 165 fbga max. 209 fbga max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v v ddq = 2.5v 6.5 7 5 pf c clk clock input capacitance 3 7 5 pf c i/o input/output capacitance 5.5 6 7 pf thermal resistance [19] parameter description test conditions 100 tqfp package 165 fbga package 209 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 25.21 20.8 25.31 c/w jc thermal resistance (junction to case) 2.28 3.2 4.48 c/w ac test loads and waveforms note: 19. tested initially and after any design or process change that may affect these parameters. output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 20 of 31 switching characteristics over the operating range [24, 25] parameter description ?250 ?200 ?167 unit min. max min. max. min. max t power v dd (typical) to the first access [20] 111ms clock t cyc clock cycle time 4.0 5 6 ns t ch clock high 1.5 2.0 2.4 ns t cl clock low 1.5 2.0 2.4 ns output times t co data output valid after clk rise 2.6 3.2 3.4 ns t doh data output hold afte r clk rise 1.0 1.5 1.5 ns t clz clock to low-z [21, 22, 23] 1.0 1.3 1.5 ns t chz clock to high-z [21, 22, 23] 2.6 3.0 3.4 ns t oev oe low to output valid 2.6 3.0 3.4 ns t oelz oe low to output low-z [21, 22, 23] 000 ns t oehz oe high to output high-z [21, 22, 23] 2.6 3.0 3.4 ns set-up times t as address set-up before clk rise 1.2 1.4 1.5 ns t ads adsc , adsp set-up before clk rise 1.2 1.4 1.5 ns t advs adv set-up before clk rise 1.2 1.4 1.5 ns t wes gw , bwe , bw x set-up before clk rise 1.2 1.4 1.5 ns t ds data input set-up befo re clk rise 1.2 1.4 1.5 ns t ces chip enable set-up before clk rise 1.2 1.4 1.5 ns hold times t ah address hold after clk rise 0.3 0.4 0.5 ns t adh adsp , adsc hold after clk rise 0.3 0.4 0.5 ns t advh adv hold after clk rise 0.3 0.4 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.3 0.4 0.5 ns t dh data input hold after clk rise 0.3 0.4 0.5 ns t ceh chip enable hold after clk rise 0.3 0.4 0.5 ns notes: 20. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 21. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in (b) of ac test loads. transition is measured 200 mv from steady-state voltage . 22. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 23. this parameter is sampled and not 100% tested. 24. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 25. test conditions shown in (a) of ac test loads unless otherwise noted. [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 21 of 31 switching waveforms read cycle timing [26] note: 26. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 22 of 31 write cycle timing [26, 27] note: 27. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 23 of 31 read/write cycle timing [26, 28, 29] notes: 28. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 29. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3 [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 24 of 31 zz mode timing [30, 31] notes: 30. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 31. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 25 of 31 ordering information not all of the speed, package and temperature ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 167 cy7c1440av33-167axc 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1442av33-167axc cy7c1440av33-167bzc 51-85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-167bzc cy7c1440av33-167bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-167bzxc cy7c1446av33-167bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-167bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free cy7c1440av33-167axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1442av33-167axi cy7c1440av33-167bzi 51-85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-167bzi cy7c1440av33-167bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-167bzxi cy7c1446av33-167bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-167bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free 200 cy7c1440av33-200axc 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1442av33-200axc cy7c1440av33-200bzc 51-85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-200bzc cy7c1440av33-200bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-200bzxc cy7c1446av33-200bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-200bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free cy7c1440av33-200axi 51-85050 100-pin thin quad fl at pack (14 x 20 x 1.4 mm) lead-free lndustrial cy7c1442av33-200axi cy7c1440av33-200bzi 51-85165 165-ball fine-pit ch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-200bzi cy7c1440av33-200bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-200bzxi cy7c1446av33-200bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-200bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 26 of 31 250 cy7c1440av33-250axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1442av33-250axc cy7c1440av33-250bzc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-250bzc cy7c1440av33-250bzxc 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-250bzxc cy7c1446av33-250bgc 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-250bgxc 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free cy7c1440av33-250axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1442av33-250axi CY7C1440AV33-250BZI 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) cy7c1442av33-250bzi cy7c1440av33-250bzxi 51-85165 165-ball fine-pitch ball grid array (15 x 17 x 1.4 mm) lead-free cy7c1442av33-250bzxi cy7c1446av33-250bgi 51-85167 209-ball fine-pitch ball grid array (14 22 1.76 mm) cy7c1446av33-250bgxi 209-ball fine-pitch ball grid array (14 22 1.76 mm) lead-free ordering information (continued) not all of the speed, package and temperature ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 27 of 31 package diagrams note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*b [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 28 of 31 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.4 mm) (51-85165) 51-85165-*a [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 29 of 31 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered tr ademarks of intel corporation. powerpc is a trademark of ibm corporation. all product and company names mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) 209-ball fbga (14 x 22 x 1.76 mm) (51-85167) 51-85167-** [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 30 of 31 document history page document title: cy7c1440av33/cy7c1442av33/cy7c1446av33 36 -mbit (1m x 36/2m x 18/512k x 72) pipelined sync sram document number: 38-05383 rev. ecn no. issue date orig. of change description of change ** 124437 03/04/03 cjm new data sheet *a 254910 see ecn syt part number changed from prev ious revision. new and old part number differ by the letter ?a? modified functional block diagrams modified switching waveforms added boundary scan information added footnote #14 (32-bit vendor id code changed) added i dd , i x and i sb values in the dc electrical characteristics added t power specifications in switching characteristics table removed 119 pbga package changed 165 fbga package from bb165c (15 x 17 x 1.20 mm) to bb165 (15 x 17 x 1.40 mm) changed 209-lead pbga bg209 (14 x 22 x 2.20 mm) to bb209a (14 x 22 x 1.76 mm) *b 306335 see ecn syt changed h9 pin from v ssq to v ss on the pin configuration table for 209 fbga on page # 6 changed t co from 3.0 to 3.2 ns and t doh from 1.3 ns to 1.5 ns for 200 mhz speed bin on the switching characteristics table on page # 19 changed ja and jc from tbd to 25.21 and 2.58 c/w respectively for tqfp package on pg # 19 replaced ja and jc from tbd to respective values for 165 bga and 209 fbga packages on the thermal resistance table added lead-free information for 100-pin tqfp, 165 fbga and 209 fbga packages changed i dd from 450, 400 and 350 ma to 475, 425 and 375 ma for frequencies of 250, 200 and 167 mhz respectively changed i sb1 from 190, 180 and 170 ma to 225 ma for frequencies of 250, 200 and 167 mhz respectively changed i sb2 from 80 to 100 ma changed i sb3 from 180, 170 and 160 ma to 200 ma for frequencies of 250, 200 and 167 mhz respectively changed i sb4 from 100 to 110 ma *c 332173 see ecn syt modified address expansion balls in the pinouts for 165 fbga and 209 fbga package as per jedec standards modified v ol, v oh test conditions changed c in , c clk and c i/o to 7, 7and 6 pf from 5, 5 and 7 pf for 165 fbga package changed i sb2 and i sb4 from 100 and 110 ma to 120 and 135 ma respectively added industrial temperature grade included the missing 100 tqfp package diagram updated the ordering information by shading and unshading mpns as per availability *d 417547 see ecn rxu converted from preliminary to final changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed i x current value in mode from ?5 & 30 a to ?30 & 5 a respec- tively and also changed i x current value in zz from ?30 & 5 a to ?5 & 30 a respectively on page# 18 modified test condition in note# 8 from v ih < v dd to v ih < v dd modified ?input load? to ?input leaka ge current except zz and mode? in the electrical characteristics table replaced package name column with package diagram in the ordering information table replaced package diagram of 51-85050 from *a to *b updated the ordering information [+] feedback
cy7c1440av33 cy7c1442av33 cy7c1446av33 document #: 38-05383 rev. *e page 31 of 31 *e 473650 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table. document title: cy7c1440av33/cy7c1442av33/cy7c1446av33 3 6-mbit (1m x 36/2m x 18/512k x 72) pipelined sync sram document number: 38-05383 rev. ecn no. issue date orig. of change description of change [+] feedback

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